Wide-Bandwidth Single-Bit Continuous-Time-Sigma-Delta-Modulation for Area- and Power-Efficient A/D Conversion with Low Jitter Sensitivity

Overview & Synopsis

Ever-increasing bandwidth demand, growing system complexity and cost pressure require to implement smart consumer devices with Analog Mixed Signal (AMS) Systems on Chip (SoCs) that are manufactured in state of the art Ultra Deep Sub-Micron (UDSM) CMOS semiconductor technologies. Continuous-Time (CT)- ∑Δ -Analog-to-Digital Converters (ADCs) have become an important interface building block of these SoCs as they provide an excellent compromise of dynamic range, bandwidth and power dissipation. These properties made CT-∑Δ-ADCs the preferred choice for radio interfaces in smartphones. However, efforts to further reduce the area and power consumption of this class of data converters are needed for future mobile devices such as wearable computers and smart sensor interfaces for the Internet of Things (IoT) that require a long battery lifetime and low production cost despite high complexity. Moreover, this improvement has to be achieved under steadily degrading properties of analog components due to shrinking feature size in digital CMOS technologies. In this work, several novel design techniques that reduce the chip size and power consumption and improve the performance and clock jitter robustness of CT-∑Δ-ADCs on architectural and transistor level are proposed with an emphasis on UDSM CMOS implementations. Two testchips have been designed and manufactured to prove these concepts: A robust mostly-analog ninth order single-bit CT-∑Δ-ADC with a very high Maximum Stable Amplitude (MSA) as a first test vehicle and finally a mostly-digital 0:039 mm2, 1:82 mW third order CT-∑Δ-ADC in 65 nm CMOS with 10 MHz bandwidth and 68:6 dB Peak Signal to Noise and Distortion Ratio (SNDRp). Using a minimalistic active analog section that consists of only ten inverters, this second testchip is one of the most compact and powerefficient wideband CT-∑Δ -ADCs published so far.