Cryogenic Recharacterization of a Commercial 22 nm FD-SOI Foundry Standard-Cell Library

Overview & Synopsis

Wiring and bandwidth bottlenecks between a quantum processor and room-temperature electronics can be reduced by placing digital control at the cryogenic stage, but commercial foundry standard-cell libraries are not specified for operation at 4 K. A cryogenic recharacterization flow is therefore developed for a commercial 22 nm FD-SOI foundry standard-cell library using commercially available cryogenic compact-device models, while retaining the original cell circuits, layouts, logic functions, and implementation semantics and remaining compatible with the commercial synthesis, place-and-route, and signoff methodology used at room temperature. Body-bias dependence is quantified over 38,640 matched slew/load points at zero, +/-0.9 V, and +/-1.8 V body bias. Relative to full bias, zero-bias operation increases the median rising and falling delays by 38.6x and 33.0x, while approximately 90% of transitions exceed the foundry-defined maximum-transition envelope. The 0.8 V-to-0.4 V level shifter is even more sensitive to body bias: its worst-case falling delay decreases from 30.6 ns at zero bias to 0.56 ns at +/-1.8 V. For the outbound 0.4 V-to-0.8 V crossing, driving the 0.8 V receiver without a level shifter dissipates 57.7 uW of static power per bit at full bias, against 0.196 nW when level-shifted. In post-route analysis of the unchanged extracted physical database of a fabricated 32-bit ALU, the register-to-register setup boundary increases from 1.3 MHz at zero bias to 37.9 MHz at +/-0.9 V and 132.9 MHz at +/-1.8 V.